1. Technical Field
The present invention relates to a process for manufacturing a multi-drain power electronic device integrated on a semiconductor substrate.
More specifically, the invention relates to a process for manufacturing a multi-drain power electronic device integrated on a semiconductor substrate of a first type of conductivity.
The invention particularly, but not exclusively, relates to a process for manufacturing a multi-drain power MOS transistor and the following description is made with reference to this field of application by way of illustration only.
2. Description of the Related Art
As it is well known, power MOS devices with a breakdown voltage BV comprised between 200 and 1000V have a high output resistance (Ron) mainly due to the resistance of the epitaxial drain layer which is used to withstand high voltages and which depends on the concentration of dopant of the epitaxial layer itself.
However, the possibility is also known of obtaining power MOS devices with a low output resistance and a high breakdown voltage BV by modifying the epitaxial layer concentration.
A known MOS device meeting this need is shown in FIG. 1, globally indicated with 3. Such a power MOS device is of the so called multi-drain type and it comprises a heavily doped semiconductor substrate 1, in particular of the N+ type, whereon a semiconductor epitaxial layer 2 of the same N type is formed.
The epitaxial layer 2 forms a common drain layer for a plurality of elementary units forming the power MOS device 3. Each elementary unit comprises a body region 4, in particular of the P type, formed on the epitaxial layer 2.
In the epitaxial layer 2, below each body region 4, there is a column region 5, in particular of the P type, which extends downwards for substantially the whole thickness of the epitaxial layer 2 towards the semiconductor substrate 1.
In particular, each column region 5 is aligned and in contact with a respective body region 4 of an elementary unit of the power MOS device 3.
In such way, as shown in FIG. 2 wherein the concentration of the epitaxial layer 2 versus its thickness is illustrated, the N epitaxial layer 2 of the power MOS device 3 thus formed has a constant resistivity. Also the column regions 5 have a constant concentration along their whole column extension, as shown in FIG. 3 wherein the concentration of the column regions 5 versus their thickness is illustrated.
The power MOS device 3 also exhibits, inside the body regions 4, heavily doped source regions 6, in particular of the N type.
The surface of the epitaxial layer 2 is thus covered with a thin gate oxide layer 7 and with a polysilicon layer 8. Openings are provided in the polysilicon layer 8 and in the thin gate oxide layer 7 to uncover portions of the epitaxial layer 2 surface aligned with each source region 6. An insulating layer 9 completely covers the polysilicon layer 8 and it partially covers the source regions 6, so as to allow a source metallic layer 10 to contact the source regions 6 and the body regions 4. A drain metallic layer 1 OA is also provided on the lower surface of the semiconductor substrate.
It is to be noted that the presence of the column regions 5 thus allows to reduce the resistivity of the epitaxial layer 2 without decreasing the breakdown voltage BV of the power MOS device 3 as a whole. With this type of devices it is thus possible to reach a predetermined breakdown voltage BV with a resistivity of the epitaxial layer being lower than that used in conventional MOS devices and, in consequence, to obtain power MOS transistors with reduced output resistance.
Moreover, as shown in FIG. 4, power MOS devices 3 formed by means of a plurality of elementary units provided with column regions 5 exhibit an output resistance, being the breakdown voltage equal, shown by the curve A, lower not only than that of conventional MOS devices, shown by the curve B, but also lower than the so called silicon ideal limit, shown by the curve C.
So as to better understand the dynamics of these known devices, with reference to Figures from 5 to 9, a method is now described by means of which the multi-drain power MOS device of FIG. 1 is formed.
In particular, on the N+ heavily doped semiconductor substrate 1 an epitaxial layer 2 is formed comprising, on the bottom, a first epitaxial layer 2a of the N type with a dopant concentration corresponding to a resistivity ρ.
After having formed a first photolithographic mask on the second epitaxial layer 2a, a trench is formed in this second epitaxial layer 2a through the first photolithographic mask for forming a zero level indicator not shown in the Figures.
A second mask is then formed on such first epitaxial layer 2a wherein a plurality of openings are formed.
Through these openings a first implant step of P dopant is carried out for forming first implanted regions 5a, as shown in FIG. 5.
As shown in FIG. 6, on the first epitaxial layer 2a a second N epitaxial layer 2b is formed with a dopant concentration corresponding to the resistivity ρ.
A third mask is then formed, aligned with the second mask by means of the zero level indicator, on the second epitaxial layer 2b wherein a plurality of openings are formed.
Through these openings a second implant step of a P dopant is carried out in the second epitaxial layer 2b for forming second implanted regions 5b. 
As shown in FIG. 7, on the second epitaxial layer 2b, a third N epitaxial layer 2c is then formed which has a dopant concentration corresponding to the resistivity ρ.
A fourth mask is then formed, aligned with the second, third mask by means of the zero level indicator, on the third epitaxial layer 2c wherein a plurality of openings are formed.
Through these openings a third implant step of P dopant is carried out in the third epitaxial layer 2c for forming, by means of a successive diffusion process, third implanted regions 5c. 
As shown in FIG. 8, on the third epitaxial layer 2c, the fourth N epitaxial layer 2d is then formed which has a dopant concentration always corresponding to the resistivity ρ.
A fifth mask is then formed, aligned with the second, third and fourth by means of the zero level indicator, on the fourth epitaxial layer 2d wherein a plurality of openings are formed.
Through these openings a fourth implant step of P dopant in the fourth epitaxial layer 2a is carried out for forming fourth implanted regions 5d. 
Obviously, it is possible to provide any number of masking steps and subsequent dopant implantation for forming a plurality of implanted regions being aligned and arranged in a succession of epitaxial layers overlapped onto each other.
As shown in FIG. 9, as last, on the fourth epitaxial layer 2d, a fifth N epitaxial layer 2e is formed having a fifth dopant concentration always corresponding to the resistivity ρ.
A sixth mask is then formed, aligned with the second, third and fourth and fifth mask by means of the zero level indicator, on the fifth epitaxial layer 2e wherein a plurality of openings are opened.
Through these openings, a fifth implant step of P dopant is then carried out in the fifth epitaxial layer 2e for forming the body regions 4 of the power MOS device 3, as shown in FIG. 1.
A seventh mask is then formed, aligned with the second, third and fourth and fifth and sixth mask by means of the zero level indicator, on the fifth epitaxial layer 2e wherein a plurality of openings are formed.
Through these openings a sixth implant step of N dopant is then carried out in the fifth epitaxial layer 2e for forming the source regions 6 of the power MOS device 3.
A diffusion thermal process is then carried out for diffusing the implanted regions 5a, 5b, 5c, 5d, the body regions 4 and the source regions 6 of the power MOS device 3 and so that the implanted regions 5a, 5b, 5c, 5d form a single column region aligned and in contact with the body region 4.
The process is then completed with the conventional process steps which include the formation of the thin gate oxide layer 7 and the polysilicon layer 8 on the surface of the epitaxial layer 2. Openings are then provided in the polysilicon layer 8 and in the thin gate oxide layer 7 until they uncover portions of the epitaxial layer 2 surface aligned with each source region 6. The insulating layer 9 is formed until it completely covers the polysilicon layer and it partially covers the source region 6, so as to allow a source metallic layer 10 formed on the power MOS device 3 to contact the source regions 6 and the body regions 4. A drain metallic layer 10A is finally formed on the lower surface of the semiconductor substrate 1.
It is to be noted that the presence of the column regions 5 hooked onto the body regions 4 empties the drain region 2, allowing the power MOS device 3 thus formed to withstand a predetermined voltage applied from the outside to the device even in presence of high concentrations of dopant in the epitaxial layer 2 (which is an conductive layer of the N type, in the case of N channel devices like the one shown with reference to FIGS. 1 and 5-9).
Moreover, the breakdown voltage BV that the power MOS device 3 thus obtained can withstand, varies, the resistivity of the epitaxial layer 2 being equal, with the dopant concentration in the column regions 5 (which are, in the example shown in FIGS. 1 and 5-9, of the P type).
In particular, as shown in FIG. 10, the breakdown voltage BV varies when the P dopant concentration in the drain epitaxial layer 2 increases: in particular, the voltage BV is the highest when the N dopant concentration in the drain epitaxial layer 2 is completely balanced by the P dopant concentration introduced by an implant P dose ΦE used for forming the column regions. This condition is indicated as “charge balance”.
If, during the first P dopant implant step for forming first implanted regions 5a an implant dose Φ lower than the implant dose ΦE is used, the final concentration of the column regions 5 is lower than the concentration of the column regions 5 obtained by means of the implant dose ΦE used in the case of “charge balance”. This condition is indicated as “p charge fault”, or, equivalently, “n charge excess”. If, during the first P dopant implant step for forming first implanted regions 5a, an implant dose Φ higher than the implant dose ΦE is used, the concentration of the column regions 5 obtained in the case of “charge balance”. This condition is indicated as “p charge excess” or, equivalently, “n charge fault”.
As it has been noted, under both the described charge excess/fault conditions, the breakdown voltage BV of the devices obtained is lower than that which is obtained by using the implant dose ΦE.
Moreover, in these devices of the multi-drain type, the resistivity of the epitaxial layer 2 sets the distance between two adjacent column regions 5 and thus the pitch of the whole power MOS device 3 thus formed. The lateral extension and the shape of the column regions 5 is in fact univocally determined by the temperature used in the diffusion thermal process for the formation of the column regions 5.
Moreover, the breakdown voltage BV the power MOS device 3 must be able to withstand defines the height of the column regions 5: for a device of 500 V it is comprised between 20 and 30 μm.
However, the area occupied by the column regions 5, useful for the cut-off step, is not used during the conduction of the power MOS device 3: the lateral widening from the column regions 5 limits in fact the electrical performances in conduction of the power MOS device 3 thus formed.
A possible solution for reducing the width of the column regions 5 and increasing the density of the elementary units, maintaining the characteristics of withstanding the high voltages of the power MOS device, it is that of containing the thermal balance during the diffusion thermal process thus decreasing the lateral diffusion of the regions 5a, 5b, 5c and 5d implanted in the epitaxial layers. However, in the diffusion thermal process with limited thermal budget to allow however the implanted regions 5a, 5b, 5c and 5d to form a single electrically continuous P column region it is necessary to reduce the thickness of each single epitaxial layer 2a, 2b, 2c and 2d wherein each one of such implanted regions 5a, 5b, 5c and 5d is formed. In reality, by reducing the thickness each single epitaxial layer 2a, 2b, 2c and 2d decreases the thickness of the drain region 2 and thus the final breakdown voltage BV the power MOS device 3 thus obtained can withstand.
By using thermal processes with reduced thermal budget and thus reduced thicknesses for the drain epitaxial layer 2, for obtaining power MOS devices which can withstand a predetermined voltage equal to that which can be obtained with devices formed with greater thermal budgets, the number of the epitaxial layers forming the drain epitaxial layer 2 and relative implant steps which form P column regions 5 is to be increased.
This solution remarkably increases the manufacturing costs of the power MOS devices 3 thus formed.